The invention relates to a transmission system for the synchronous digital hierarchy, comprising an adaptation circuit for compensating for phase variations of an STM-N signal.
In such a transmission system for the synchronous digital hierarchy, plesiochronous signals are combined by means of multiplexing and transmitted over an optical transmission path. Two digital signals are called plesiochronous when their bit rates deviate from the nominal value within given tolerance limits. The signals are combined according to a certain pattern and structured in frames. An example is the referenced synchronous transport module STM-N, specifically described in the CCITT Recommendations "Recommendation G.707, G.708 and G.709".
The structure of an STM-1 frame is diagrammatically represented in FIG. 1a. The frame comprises 270 columns and 9 rows. Each column of a row contains 1 byte. The rows 1 to 3 and 5 to 9, in the columns 1 to 9 accommodate the so-called Section Overhead (SOH) for control and error detection information signals, the fourth row of columns 1 to 9 accommodates an Administrative Unit referenced AU pointer (AU-P), and the remaining columns and rows accommodate the actual useful information referenced "STM-1-Payload" (P). As shown in FIG. 1b, the STM-1-Payload accommodates, for example, a Virtual Container VC-4 consisting of a Payload and a Path Overhead (POH). A container is here to be understood as the basic unit of payload. Such a container may comprise still further containers.
A state-of-the-art multiplexing structure for the STM-N frames is shown in FIG. 2. For example, C-4 data of a payload are inserted into a container at a bit rate of 140 Mbit/s. The addition of the POH renders the container C-4 into a virtual container VC-4. The addition of justification bytes and further bytes renders the virtual container VC-4 into an administrative unit AU-4. The container VC-4 may also be formed by a combination of several containers C-12. Data of a payload are inserted into such a container C-12 at a bit rate of 2 Mbit/s. The addition of a POH renders such a container C-12 into a virtual container VC-12. The virtual container VC-12 becomes a tributary unit TU-12 as a result of the addition of justification bytes and further bytes. These TUs are combined to groups TUG-2 and TUG-3 respectively.
STM-N signals are transmitted over a transmit path which comprises circuits at certain distances in which circuits, for example, a clock recovered from the STM-1 signal is adapted to a locally standardized clock. Even when various signals to be transmitted are combined to a single STM-N signal (for example, four STM-1 signals are combined to one STM-4 signal), their clocks are adapted to one another. On the receiver side of the transmission system, at the end of the optical transmit path, the STM-N signal is again subdivided into separate signals with a lower bit rate.
When a plurality of STM-1 signals are combined to one STM-4 signal and clocks in a regenerator circuit are adapted, problems of clock alignment may occur, as is described, for example, in the paper entitled "Jitter bei der Ubertragung plesiochroner Signale in der SDH" by M. Robledo and R. Urbanski, PKI Techn. Mitt. 3/1989, pp. 31 to 38. As a result of phase wander or slight frequency deviations, the individual clocks of the various STM-1 signals are no longer adapted to one another. A clock alignment is effected by means of a byte justification method. According to this method predetermined positive or negative justification locations are filled with justification bytes. With a positive justification opportunity the payload is omitted from the justification location. This justification location otherwise carries a payload. With a negative justification opportunity a payload is transmitted in the justification location. This justification location otherwise carries no payload. A justification opportunity is also denoted a pointer action.
After a plurality of adaptation circuits in which clocks are adapted have been passed through, an increasing number of pointer actions may occur. This may result in an overflowing buffer on the receiver side of the transmission system when this buffer has not been selected sufficiently large. Data loss will then occur. The buffer in a circuit on the receiver side of the transmission system is used for adapting the data to the local clock. For example, a plurality of successive justification locations might occur, causing the buffer to overflow. In order to avoid such an overflow, the buffer could be selected large enough. However, this is undesired because the overall transmission system is consequently extended and the delay of the data increased.